Job Title:
Standard Cell / GPIO Design Engineer (2 nm Technology Node)
Team: Enablement / Foundation IP Development
Location: Albany (NY), Santa Clara (CA), or Tokyo (Japan)
Overview
Rapidus Corporation is developing next-generation semiconductor technologies at the 2 nm node and beyond.
We are seeking skilled engineers to join our Foundation IP Design Team, focusing on Standard Cell and GPIO (General Purpose I/O) development.
Engineers with expertise in circuit design, layout, reliability, or DTCO are all welcome.
This position involves close collaboration with process, device, and enablement teams to deliver high-quality, high-performance IP that supports leading-edge logic technologies.
Key Responsibilities
- Design and optimize standard cells and GPIO circuits (input/output buffers, level shifters, ESD structures, and special cells) for advanced technology nodes.
- Perform transistor-level circuit design and HSPICE simulations for performance, leakage, and robustness verification across PVT corners.
- Collaborate with layout engineers to ensure design rule compliance, area efficiency, and manufacturability.
- Work with process integration and DTCO teams to co-optimize transistor architectures, layout patterns, and reliability structures.
- Support characterization and model generation for timing, power, and noise modeling.
- Participate in ESD and latch-up design verification, ensuring compliance with foundry reliability standards.
- Analyze silicon test results and feedback for model correlation and IP quality improvement.
- Cooperate with EDA vendors and PDK teams to validate design enablement and sign-off flows.
Required Qualifications
- B.S. or M.S. in Electrical Engineering, Electronics, or Microelectronics.
- 3+ years of experience in standard cellI/O, or custom circuit design for advanced CMOS nodes (= 5 nm preferred).
- Strong understanding of CMOS device behavior, low-power design techniques, and circuit optimization.
- Hands-on experience with EDA tools for schematic design, simulation, and layout verification (e.g., Cadence Virtuoso, HSPICE, Calibre).
- Familiarity with DRC/LVS/EMIR verification flows and reliability checks.
- Strong problem-solving, analytical, and cross-functional collaboration skills.
- Effective communication and documentation skills in English.
Preferred Qualifications
- Experience with nanosheet / GAA transistor architectures or FinFET-based IP design
- Familiarity with DTCO and library automation / QA flows (Python, TCL, etc.).
- Experience with test-chip development or IP qualification (Level-1 / Level-2).
- Knowledge of characterization tools (Liberate, SiliconSmart) and Liberty model validation
- Understanding of ESD protection, latch-up prevention, and pad ring integration
- Japanese language proficiency is a plus.
