Sandia National Laboratories is seeking a Digital Verification Engineer (R&D Electrical Engineer) with expertise in formal verification tools to ensure the correct functionality of ASIC and FPGA designs. The ideal candidate will have hands-on experience with VHDL and Verilog design languages and be proficient in using SystemVerilog Assertions (SVA) within formal verification environments.
Success in this role requires a strong foundation in digital design principles, a detail-oriented and logical approach to problem-solving, and excellent written communication skills.
As a Digital Verification Engineer, you will:
- Translate digital design requirements at various development stages into precise, unambiguous checks against the implementation.
- Adapt diverse requirementsincluding functionality, safety, and information protectioninto SystemVerilog Assertions (SVA) for verification.
- Evaluate trade-offs in formal analysis complexity to ensure verification tasks remain tractable and efficient.
- Collaborate closely with designers, system engineers, and other verification specialists to deploy systems that are verifiably correct.
- Produce clear, concise, and well-documented archival reports detailing verification activities and results.
- Present verification findings at technical reviews to peers and customers.
- Continuously learn and apply new formal verification techniques and methodologies.
While this position is ideally based on-site in California or New Mexico with hybrid flexibility, remote work from any U.S. State may be considered. Candidates working remotely must be able to travel to the California site approximately once per month to support mission needs.
Applicants on this requisition may be interviewed by multiple organizations at Sandia National Laboratories.
